NXP Semiconductors /LPC43xx /EEPROM /WSTATE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as WSTATE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PHASE30PHASE20PHASE10RESERVED0 (LCK_PARWEP)LCK_PARWEP

Description

EEPROM wait state register

Fields

PHASE3

Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3.

PHASE2

Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2.

PHASE1

Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1.

RESERVED

Reserved. Read value is undefined, only zero should be written.

LCK_PARWEP

Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access

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